In contrast, under a write update protocol, when one PE writes new data to the coherence granule, all other PEs receive a copy of the new data, and update their respective local copies of the coherence granule using the new data. A PE that loses a cached copy of the coherence granule in this manner may subsequently re-obtain a copy of the coherence granule via a memory load operation after the memory store operation that triggered the invalidation is completed. Under a write invalidate protocol, when one PE writes to a coherence granule (a subdivision of the system memory representing an aligned size in bytes on which cache coherence is managed), all copies of the coherence granule stored in the local caches of the other PEs are invalidated, with dirty (i.e., modified) copies of the coherence granule being written to the system memory before being invalidated. In this manner, conflicts that may arise between the PEs due to inconsistencies between local copies of the shared data can be avoided.Ĭonventional cache coherence protocols include write invalidate protocols and write update protocols.

Thus, to ensure that all of the PEs have a consistent view of the shared data, the processor-based device provides support for a cache coherence protocol to enable local changes to the shared data within one PE to be propagated to other PEs. Because the multiple PEs of the processor-based device may share a memory resource such as a system memory, multiple copies of shared data read from a given memory address may exist at the same time within the system memory and within the local caches of the PEs. BACKGROUNDĪ processor-based device may include multiple processing elements (PEs) (e.g., processor cores, as a non-limiting example) that each provide one or more local caches for storing frequently accessed data. The technology of the disclosure relates to cache coherence protocols in processor-based devices, and, more particularly, to dynamic selection of cache coherence protocols.

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